Enabling True Design for Manufacturability

Without any doubt, Design For Manufacturability has been the hottest buzzword for the last couple of years. This is quite justifiable by the enormous challenges in nanometer technology nodes and ever increasing design-process interactions. As a result, virtually all EDA companies have focused on providing the “DFM Solutions”. Since the concept of DFM covers an extremely broad spectrum of tasks from the system level all the way to the manufacturing process, many of these DFM solutions are just the re-labeled design verification tasks. In this talk, we will provide a more thorough classification of various DFM activities with the emphasis on the design tasks. We will also discuss the necessary condition to enable true DFM, i.e., the comprehensive characterization of the design-process interactions. We will present a complete process characterization methodology that is capable of extracting all the salient process variations for a full set of product design attributes. We will illustrate our talk by showing the yield loss Pareto for the leading technology nodes that will cover all the dominant yield loss phenomena including random, systematic and parametric mechanisms. We will also demonstrate example of design flows that take advantage of such a comprehensive characterization together with silicon results demonstrating the advantages of true DFM.